DDR SDRAM and Memory Modules

Synchronous dynamic RAM stores charge in cells selected through a hierarchy of channels, ranks, banks, rows, and columns. DDR SDRAM adds transfers on both edges of the data clock, but the name of a DDR generation denotes a complete electrical and command protocol. DDR3, DDR4, and DDR5 modules are therefore not interchangeable even when their capacities match.

From Cells to Memory Channels #

Each DRAM die divides its cell array into banks. A bank has many rows, and its sense amplifiers also serve as a row buffer. Opening a row copies its cells into that buffer; a later column selection chooses a subset for transfer. DDR4 divides banks into bank groups because some command-to-command delays differ within and across groups.

Several terms describe different levels of the hierarchy:

• A component is one DRAM package. Widths such as x4, x8, and x16 state how many DQ data bits the component supplies per transfer.
• A rank is a group of components selected together. Eight x8 components form one 64-bit rank; a ninth supplies eight check bits on a 72-bit ECC module.
• A module is the DIMM or SO-DIMM circuit board that carries one or more ranks. Rank count does not follow the number of populated board sides.
• A channel is an independently scheduled memory-controller interface. A conventional non-ECC channel transfers 64 data bits at a time.

Capacity and width must not be conflated. An 8-Gib x8 component stores 1 GiB while exposing eight data pins. Eight such components provide a 64-bit-wide, 8-GiB rank:

8 Gib/component × 8 components ÷ 8 bits/byte = 8 GiB

A second equivalent rank raises module capacity to 16 GiB. ECC components add check bits rather than application-visible bytes.

The Row Command Sequence #

The controller operates a bank through an explicit state machine:

1. ACTIVATE selects a bank and row and loads that row into the sense amplifiers.
2. READ or WRITE selects a column in the open row and starts a burst.
3. More column commands may reuse the open row.
4. PRECHARGE restores the cells and closes the row before another row in the same bank can be activated.

Read or write commands can request auto-precharge, which closes the bank after the burst. Refresh commands restore charge without software enumerating rows; the memory controller issues them often enough to meet the device’s retention requirements.

Timing symbols describe constraints between commands and data, not one scalar measure of memory speed:

A row hit avoids tRP and tRCD; a row conflict pays both before useful data can move. The controller interleaves work across banks and ranks to cover some delays, although every rank on a channel ultimately shares the channel’s data wires.

Bursts, Prefetch, and Marketed Rates #

DDR SDRAM does not return one independently addressed byte per command. A column command initiates a burst, and a DDR4 burst length of eight transfers matches its 8n-prefetch architecture. The core array supplies a wider group to an I/O buffer, which serializes that group over faster external pins. Prefetch width therefore describes internal-to-external organization; it is not the module’s channel width.

DDR data rate is measured in transfers per second. DDR4-3200 uses a 1600 MHz I/O clock and transfers on both edges, thus its marketed rate is 3200 MT/s rather than 3200 MHz. Peak bandwidth follows from transfer rate and channel width:

3200 × 10^6 transfers/s × 64 bits/transfer ÷ 8 = 25.6 GB/s

Two independently used 64-bit channels can provide 51.2 GB/s at the same rate. Refresh, command slots, bus turnarounds, row misses, and workload locality reduce sustained bandwidth; latency timings remain relevant even when two modules advertise the same MT/s rating.

DDR4 Command, Address, and Data Interfaces #

DDR4 separates command/address signaling from the bidirectional data interface. Differential CK_t/CK_c clocks sample command and address signals. Chip-select, bank-group, bank, address, and control pins encode operations and identify the target rank and location; ACT_n distinguishes activation from other command encodings.

DQ pins carry data, while differential DQS_t/DQS_c strobes provide source- synchronous timing for each byte lane. Depending on component width and mode, DM_n masks write data and DBI_n signals data-bus inversion. Other signals serve protocol and electrical control:

• CKE participates in clock and power-state control.
• ODT selects on-die termination.
• ZQ supports impedance calibration.
• RESET_n, parity, and ALERT_n support initialization and error reporting where the device or module type defines them.

Mode-register writes configure burst behavior, latencies, termination, power features, and related options. Initialization must follow the component data sheet because supply, reset, mode-register, and ZQ-calibration ordering are timing requirements rather than suggestions.

Modules, Ranks, and Platform Limits #

DIMM means dual inline memory module: contacts on opposite faces carry distinct signals. DDR4 UDIMMs have 288 contacts, and DDR4 SO-DIMMs have 260. Key positions, voltages, pin assignments, and protocols differ across generations.

An unbuffered DIMM connects command/address lines directly to its DRAM loads. A registered DIMM inserts a register on selected control paths, which permits more devices per channel at the cost of an additional command stage. Platform firmware must also understand module type, rank topology, supported speeds, and timing data from the module’s serial-presence-detect EEPROM.

Memory-controller and motherboard limits determine whether a module can operate at its label rate. DDR4-3200 states 3200 MT/s, while PC4-25600 expresses the corresponding 25.6 GB/s peak for one 64-bit data path. Neither label guarantees that all populated channels will train at that rate.

References #

• JEDEC DDR4 SDRAM standard, JESD79-4
• JEDEC DDR4 module standards catalog
• Micron DDR4 SDRAM product documentation