x86 Architectural Registers

x86 アーキテクチャレジスターは、プログラマーから見える整数、制御、状態、アドレス変換、デバッグ、浮動小数点、ベクトルの状態を保持します。 幅と利用可能性は実行モードと有効な拡張に依存します。呼び出し規約はこれらのレジスターの一部にソフトウェア上の役割を割り当てますが、 アーキテクチャ上の動作は変えません。

汎用レジスターとサブレジスター #

IA-32 exposes EAX, EBX, ECX, EDX, ESI, EDI, EBP, and ESP. x86-64 widens them to RAX through RSP and adds R8 through R15. サブレジスターは同じアーキテクチャレジスターの一部に名前を付けます。

• RAX は 64 ビット、EAX は下位 32 ビット、AX は下位 16 ビットであり、 AL and AH name low and high bytes of AX.
• Writing a 32-bit destination in 64-bit mode clears the upper 32 bits.
• Writing a 16-bit or 8-bit destination preserves the other bits.
• A REX prefix makes SPL, BPL, SIL, and DIL available but prevents an instruction from encoding AH, BH, CH, or DH.

RIP は 64 ビット命令ポインターで、32 ビットコードでは EIP を使います。 通常の MOV では書き込めず、分岐、呼び出し、リターン、例外、割り込みリターンが制御フローを変更します。 RSP は現在のスタックポインターです。

Register purpose at a function boundary comes from an ABI. System V AMD64 uses RDI, RSI, RDX, RCX, R8, and R9 for initial integer arguments, whereas Microsoft x64 uses RCX, RDX, R8, and R9. RBP can serve as a frame pointer but may be available as a general register when the ABI and unwind information permit. A Linux syscall uses another register convention, so function-call and kernel-entry roles must not be conflated.

RFLAGS #

RFLAGS extends the older EFLAGS and FLAGS registers. 一般的な算術状態ビットは次のとおりです。

Control and system bits include:

• DF, which chooses incrementing or decrementing indexes for string instructions.
• IF, which controls delivery of maskable interrupts subject to privilege and virtualization rules.
• TF, which requests a debug trap after an instruction.
• IOPL, which participates in port-I/O and selected interrupt-control checks.
• NT, which records nested hardware-task state in legacy protected mode.
• RF, VM, AC, VIF, VIP, and ID, whose meanings depend on mode and enabled facilities.

Instructions define which flags they write, preserve, or leave undefined. PUSHF/POPF, interrupt entry, and return operations also apply privilege restrictions; software cannot assume every visible bit can be changed at its current CPL.

セグメントレジスターと隠しディスクリプターキャッシュ #

CS、SS、DS、ES、FS、GS には可視セレクターと隠しディスクリプター状態があります。 プロテクトモードでセレクターをロードするとディスクリプターを取得し、そのベース、リミット、型、アクセス権をキャッシュします。 ディスクリプターテーブルを編集しても、ロード済みのキャッシュは更新されません。

In 64-bit mode, normal address generation ignores the bases and limits of CS, SS, DS, and ES. FS and GS retain 64-bit bases set through model-specific registers or supported instructions, which operating systems use for thread-local and per-CPU data. Selector and descriptor rules still apply where the architecture specifies them.

GDTR and IDTR hold a linear base and byte limit for the global descriptor table and interrupt descriptor table. LDTR and TR hold selectors plus cached descriptors for the local descriptor table and task-state segment. LGDT, LIDT, LLDT, and LTR establish those values under privilege checks. x86 Protected Mode and Privilege describes the table formats and transitions.

制御レジスターとシステムレジスター #

制御レジスターは実行とアドレス変換を設定します。

• CR0 はプロテクトモード、ページング、書き込み保護、キャッシュ、選択した numeric-state controls.
• CR2 receives the linear address associated with a page fault.
• CR3 selects the paging-structure root and can carry a process-context identifier when PCID is enabled.
• CR4 enables architectural facilities such as PAE, global pages, OS-managed SIMD state, SMEP, SMAP, and protection keys when supported.
• CR8 controls the task-priority threshold for external interrupts in 64-bit mode.

Model-specific registers (MSRs) provide additional controls, including EFER for long-mode and no-execute enablement, system-call targets, FS/GS bases, memory types, and performance monitoring. The exact MSR set is model-dependent and must be discovered or selected from vendor documentation. RDMSR and WRMSR are privileged.

デバッグレジスター #

DR0 through DR3 hold linear breakpoint addresses. DR7 enables breakpoints and selects execution, write, or data-access conditions with supported lengths. DR6 reports why a debug exception occurred. Reserved encodings and general- detect behavior are architecture-specific, so a debugger or kernel must sanitize values before restoring untrusted debug state.

Software breakpoints instead replace an instruction byte with INT3. Hardware debug registers avoid changing code but provide only a small number of slots. Debug exceptions interact with single stepping, task switching, virtualization, and transactional execution.

x87、MMX、SIMD、マスクレジスター #

The x87 floating-point unit exposes an eight-entry register stack plus control, status, tag, instruction-pointer, and data-pointer state. MMX aliases the low 64-bit storage of the x87 registers, which is why legacy MMX code executes EMMS before returning to x87 operations.

SSE introduced XMM registers. AVX extends their low storage into YMM; AVX-512 extends it into ZMM and adds opmask registers K0 through K7. Architecture and mode determine how many registers are visible. Writing a legacy SSE destination can preserve upper vector state, while VEX- and EVEX-encoded operations apply their specified upper-bit clearing behavior. Mixing forms can therefore create dependencies or transition penalties on selected processors.

MXCSR controls SIMD floating-point rounding, exception masks, status, and denormal handling. Opmask registers govern per-lane AVX-512 merging or zeroing. Additional extensions can add tile or other state that is not represented by the original floating-point save formats.

拡張状態の管理 #

FXSAVE and FXRSTOR cover x87, MMX, SSE, and related control state. The XSAVE family uses XCR0, CPUID enumeration, and a component bitmap to manage an extensible state area. Supervisor components can use additional control and save mechanisms.

オペレーティングシステムは、安全に初期化、保存、復元、公開できる状態コンポーネントだけを有効にする必要があります。 ユーザーソフトウェアは AVX 以降の命令を実行する前に、プロセッサーの対応と OS の有効化の両方を確認します。 コンテキスト切り替えポリシーは状態を即時保存することも対応する最適化を使うこともできますが、 各スレッドから見えるアーキテクチャ状態は分離されたままでなければなりません。