RISC-V Architecture Introduction

RISC-V is an open instruction set architecture organized as a base integer ISA plus separately versioned extensions. The ISA defines instruction behavior and privileged execution; a platform profile, ABI, and execution environment add the requirements needed to run interoperable software.

Base Integer ISA and Register Convention #

RV32I and RV64I provide 32-bit and 64-bit integer registers respectively. Both define thirty-two general-purpose registers, x0 through x31. x0 always reads as zero and discards writes. The program counter is architecturally visible through control-flow effects rather than as a general-purpose register.

RISC-V uses a load-store design. Integer arithmetic reads register operands and writes a register; loads and stores move values between registers and memory. The base ISA uses fixed 32-bit encodings. RV64I adds 64-bit registers and operations plus sign-extending *W operations on low 32-bit values; it is not only RV32I with wider addresses.

The standard integer calling convention assigns ABI names and roles:

Floating-point and vector calling conventions add their own rules. Assembly that interoperates with compiled code must follow the complete psABI, including stack alignment, preserved state, relocations, and code models.

Extensions, ISA Strings, and Profiles #

Single-letter standard extensions include M for integer multiply/divide, A for atomics, F and D for floating point, C for compressed instructions, and V for vectors. Multi-letter extensions cover narrower facilities and are separated by underscores where the ISA-string grammar requires it. Extension versions matter because ratification and later revisions can change the precise contract.

The historical G abbreviation denotes a general-purpose extension set centered on IMAFD plus required dependencies. A string such as rv64gc is convenient but does not communicate every platform facility, ABI, or privileged feature. Toolchains canonicalize extension order and expand dependencies; use their -march diagnostics rather than constructing ambiguous strings.

The C extension provides 16-bit encodings for frequent operations, improving code density. Compressed instructions execute with the semantics of their defined operations and can be interleaved with longer encodings. Instruction alignment and branch targets must honor the extensions implemented by the target.

A RISC-V profile selects a named set of mandatory and optional ISA features for a class of systems. An implementation can also expose custom extensions. Portable software should target a profile or explicit extension set supported by both the hardware and execution environment rather than assuming every RV64 processor implements the same ISA.

Privilege Modes, CSRs, and Traps #

The privileged architecture defines machine mode (M), supervisor mode (S), and user mode (U). M-mode is mandatory and controls the machine. S-mode supports operating systems and virtual memory, while U-mode supports applications. Optional virtualization adds hypervisor-controlled variants and two-stage translation.

Control and status registers (CSRs) hold trap state, interrupt enables, address translation controls, counters, and extension-specific state. CSR addresses encode access and privilege constraints. An instruction that lacks permission traps rather than silently accessing a more privileged register.

A trap records a cause, exception PC, and selected status, then transfers to the configured trap vector. Delegation registers can route selected traps from M-mode to S-mode. ECALL requests a service from the execution environment, and MRET or SRET performs a checked return from a privileged handler.

Supervisor software should not depend on vendor-specific M-mode firmware calls. The Supervisor Binary Interface (SBI) defines a portable interface for services such as timer programming, interprocessor interrupts, hart management, system reset, and firmware-assisted performance monitoring. SBI is an execution environment interface, not an instruction-set extension.

Virtual Memory and Translation Fences #

S-mode translation schemes include Sv32 for RV32 and schemes such as Sv39, Sv48, and Sv57 for RV64. Page-table entries carry validity, read/write/execute, user, accessed, dirty, and other attributes. The active scheme and root are selected through satp.

Page-table writes do not automatically make all cached translations coherent. SFENCE.VMA orders relevant page-table updates and invalidates address- translation cache entries in its specified scope. Multiprocessor shootdown also requires coordination with remote harts, commonly through an SBI or platform-specific interprocessor-interrupt path.

Memory Ordering, Fences, and Atomics #

The base RISC-V weak memory model allows observations that differ from program order when dependencies or synchronization do not forbid them. FENCE orders selected predecessor and successor classes, while FENCE.I coordinates data writes with later instruction fetches on the executing hart.

The A extension provides load-reserved/store-conditional operations and atomic memory operations. Acquire (aq) and release (rl) bits add ordering to an atomic operation; aqrl supplies both directions. Atomicity and ordering solve different problems: an indivisible counter update does not publish unrelated data unless the required ordering is also present.

Language-level atomics should be preferred in C, C++, and Rust because the compiler maps their memory model to an available RISC-V sequence. Hand-written assembly must account for the extension set, memory and I/O domains, reservation failure, and forward-progress rules.

Primary References #

• RISC-V Unprivileged ISA Specification
• RISC-V Privileged Architecture Specification
• RISC-V ABIs Specification
• RISC-V Supervisor Binary Interface Specification