x86 and x86-64 Architecture Overview

x86 began with Intel’s 16-bit 8086. The 80286 introduced protected mode, IA-32 established the 32-bit programming model and paging, and AMD64 extended the architecture to 64-bit execution. Intel calls the combined architecture Intel 64 and IA-32; AMD documentation uses AMD64. Vendor names do not determine every feature, so software must discover extensions explicitly.

Byte Order and Operand Sizes #

x86 addresses memory in bytes and stores multibyte integers in little-endian order: the least-significant byte occupies the lowest address. For the 32-bit value 0x12345678 beginning at address p, memory contains:

text

address    p     p+1   p+2   p+3
byte       78    56    34    12

Architectural terminology names a 16-bit value a word, a 32-bit value a doubleword, a 64-bit value a quadword, and a 128-bit value a double quadword. Those names are independent of a C implementation’s type sizes.

Instruction operand size depends on execution mode, prefixes, opcode, and REX, VEX, or EVEX fields. In 64-bit mode, many integer instructions still default to 32-bit operands; a REX.W encoding selects 64 bits where supported. Address size is a separate attribute and controls effective-address calculation.

Ordinary integer loads and stores permit unaligned addresses, but crossing a cache-line or page boundary can increase latency or fault behavior. Atomicity guarantees depend on alignment, width, memory type, and instruction, so shared data should satisfy the architecture’s explicit requirements.

Execution Modes #

After reset, an x86 processor starts in real-address mode. Firmware establishes the tables and control registers required for later modes.

Real-address mode uses the 8086-style segment model without protected-mode privilege enforcement.
Protected mode supports 16- or 32-bit code and data segments, descriptor checks, four privilege levels, and optional paging.
Virtual-8086 mode runs real-mode-style 8086 software as a protected-mode task under operating-system control.
Long mode contains 64-bit mode and compatibility mode. Compatibility mode executes protected 16- or 32-bit code under a 64-bit operating system.
System-management mode is a separate firmware environment entered by a system-management interrupt rather than an application execution mode.

In 64-bit mode, ordinary address generation treats CS, DS, ES, and SS bases as zero and does not enforce their legacy limits. FS and GS retain usable bases, commonly for thread-local and per-CPU state. Descriptor types and privilege checks remain relevant even though flat addressing removes most segment arithmetic.

Logical, Linear, Virtual, and Physical Addresses #

Intel terminology calls a segment selector plus offset a logical address. Segmentation validates the access and adds the segment base, producing a linear address. When paging is disabled, the linear address maps directly to a physical address subject to architectural width and platform behavior. When paging is enabled, page tables translate the linear address to a physical address.

Operating-system documentation often calls a process-visible linear address a virtual address. Thus “linear” and “virtual” can refer to the same numeric address at the paging boundary, but they emphasize different models. A guest under virtualization can add another translation from guest physical to host physical memory.

An instruction forms an effective offset from base and index registers, a scale, and a displacement. In 64-bit mode, a linear address must be canonical for the enabled address width. A noncanonical address faults before ordinary paging translation. Page tables then apply present, writable, user/supervisor, execute-disable, and other permissions.

Exceptions, Interrupts, and Control Transfer #

The interrupt descriptor table maps vectors to gates. Processor-detected exceptions, software interrupt instructions, and external interrupts use those vectors, although interrupt-controller routing is platform-specific.

Exceptions are conventionally grouped as:

A fault reports before architectural completion and can often restart the instruction after correction, as with a page-not-present fault.
A trap reports after the triggering instruction, as with a breakpoint.
An abort reports a condition for which reliable restart is not generally available.

The vector determines whether the processor pushes an error code and what saved state is available. A privilege-changing gate also switches stacks according to the task-state segment. Return uses IRET or a system-call-specific return instruction after software validates the destination state.

Near branches change the instruction pointer within the current code segment. Far transfers and gates can load a new code segment and perform additional checks. SYSCALL/SYSRET and SYSENTER/SYSEXIT provide faster configured paths, but their register convention belongs to an operating-system ABI.

Extension and Operating-System Discovery #

CPUID reports vendor identification, topology information, address widths, cache parameters, and feature bits through numbered leaves and subleaves. Software must first determine the maximum supported leaf and then test every feature it intends to use. A family or model number can select an optimization after correctness has been established through feature bits.

Some features require operating-system management in addition to processor support. For AVX-family state, software checks CPUID for XSAVE and OSXSAVE, then uses XGETBV to confirm that the operating system enabled the required XCR0 components. AVX-512 and newer state can require additional bits. Similar principles apply to supervisor features, where a user-visible CPUID bit does not grant privilege.

Feature use must also account for ABI and deployment policy. A compiler’s baseline target can differ from the machine running the build, so portable binaries use a conservative baseline, function multiversioning, or runtime dispatch.