CPU 架构概览

处理器实现指令集架构（ISA）：该契约定义 defines instructions, registers, data types, address formation, exceptions, and privilege behavior. A microarchitecture implements that contract with pipelines, execution units, caches, predictors, and internal queues. Programs observe architectural state; performance depends on microarchitectural state.

从取指到提交 #

At a conceptual level, a processor fetches instruction bytes, decodes an instruction, obtains operands, executes the operation, accesses memory when required, and commits the result. A simple processor can perform those steps sequentially. A pipelined processor overlaps steps from several instructions, thus improving throughput without requiring every instruction to have low latency.

Architectural state includes general-purpose registers, status registers, the program counter, and architecturally visible memory. Microarchitectural state includes decoded-operation caches, physical registers, reorder buffers, branch history, and cache replacement metadata. A context switch must preserve the architectural state promised by the ABI; it neither saves nor exposes every internal predictor or pipeline entry.

Pipelines must handle three classes of dependency:

• Data hazards arise when one operation consumes a result that another has not produced.
• Structural hazards arise when operations contend for an execution unit, port, queue, or cache resource.
• Control hazards arise because a branch can change the next fetch address.

Forwarding supplies a result before register write-back. Register renaming maps architectural names onto a larger physical register set, thereby removing false write-after-read and write-after-write dependencies. A reorder buffer lets independent operations execute out of order while retiring completed operations in an order that preserves precise architectural exceptions.

超标量与推测执行 #

A superscalar front end can decode or issue several operations per cycle. Dispatch width is only one limit: true dependencies, execution-port pressure, cache misses, and retirement width can reduce sustained throughput.

Branch prediction chooses a likely control-flow path before the branch resolves. A correct prediction keeps the pipeline supplied; a misprediction discards younger speculative work and restarts fetch at the resolved target. Speculation must not commit incorrect architectural state, although transient execution can affect caches and other shared microarchitectural resources. Isolation code must therefore follow platform guidance for transient-execution vulnerabilities rather than relying only on architectural privilege checks.

缓存层次结构与内存延迟 #

Processor cores reach DRAM through a hierarchy because fast storage is expensive and physically constrained. L1 instruction and data caches are small and close to a core. Larger L2 and last-level caches trade latency for capacity. Cache lines transfer adjacent bytes together, so sequential access exploits spatial locality and reuse exploits temporal locality.

A cache divides addresses into tags, set indexes, and line offsets. Associativity allows more than one line in a set, reducing conflict misses at the cost of tag comparison and replacement complexity. Hardware prefetchers can hide predictable latency, but pointer chasing and capacity misses still expose lower-level cache or DRAM delays.

Multicore systems use a coherence protocol to coordinate cached copies of the same line. Coherence establishes an order for writes to one location; a memory consistency model defines the allowed ordering among different accesses. Correct concurrent software must use language atomics, locks, or other synchronization because cache coherence does not make unsynchronized compound operations atomic.

Virtual-memory hardware translates virtual addresses through page tables. Translation lookaside buffers cache recent translations; thus a TLB miss adds a page-table walk even when the data itself is cached. NUMA systems add another distance: a core can reach local memory with lower latency or higher bandwidth than memory attached to another socket.

核心、线程与 SIMD #

A core contains one or more architectural execution contexts. Simultaneous multithreading (SMT) lets hardware threads share a core’s front end, caches, and execution resources. SMT can fill otherwise idle issue slots, but contention can also reduce per-thread performance. Operating-system threads are scheduling objects and can outnumber both cores and hardware threads.

Multiple cores execute independent instruction streams. Shared-memory programs must still account for synchronization, cache-line contention, and false sharing. Adding cores does not accelerate a serial dependency chain.

SIMD instructions apply one operation to several lanes in a vector register. x86 provides SSE, AVX, and AVX-512 families; Arm and RISC-V provide their own vector facilities. A nominal vector width describes architectural state, not latency or throughput. Compilers need aliasing, alignment, dependency, and target feature information before they can vectorize safely.

汇编语法与 ABI 边界 #

汇编语法是工具约定，而不是 ISA 属性。 x86 Intel syntax places the destination first:

mov rax, rbx

AT&T syntax places the source first, prefixes registers with %, and places an operand-size suffix on many mnemonics:

movq %rbx, %rax

NASM uses Intel syntax, while GNU objdump -d defaults to AT&T syntax and accepts -Mintel. Other architectures have their own syntaxes and tool-specific directives. Syntax also does not define a calling convention: argument registers, callee-saved state, stack alignment, and object format belong to an ABI. See NASM for an assembler workflow.